Low-Kickback-Noise Preamplifier-Latched Comparators Designed for High-Speed & Accurate ADCs

High-resolution high-speed comparators are one of the main cores in the implementation of the high-performance systems, such as ADCs. Two comparators are presented in this paper where both of the structures are suitable for high-speed, low-noise and accurate applications. The comparators are designed, based on the positive feedback structure of two back-to-back inverters. An improved rail-to-rail folded cascode amplifier with an active bias circuit is utilized for the first architecture, in which the structure of the comparator is rearranged appropriate to the running comparison phase. Distinguished by its novel data reception style, a new comparator is proposed in the next circuit. In this structure, the hot n-well concept is considered for the PMOS transistors of the positive feedback latch. Applying the inputs to the bulks of the mentioned PMOS devices, isolates the regenerative outputs from the input signals; hence, a sizable attenuation in the kickback noise value is resulted. Merging the reset, evaluation and latch sequences makes it possible to decrease the comparison duration. Both of the proposed comparators of this paper benefits from this excellence, therefore an intensive increase is observed in their comparison speed. In order to confirm the performance accuracy of the circuits in various terms, multiple simulations are performed in all process corners, using HSPICE (level49) with a standard 0.35μm CMOS process and the power supply of 3.3V. VDD noise of 300mVp-p and alterations in temperature are also included in the simulation conditions. The simulation results confirm recognition of a differential input with 2mV pick-to-pick amplitude at as high a clock frequency as 800MHz with power consumption about 2.6mW for the first circuit and a 1mV differential input with update rate of 1GHz and power consumption about 1.6mW for the low-noise structure of the second comparator. According to the layout pattern, an active area of 55μm × 13μm and 24μm × 15μm is occupied by the improved folded cascode comparator and the proposed novel structure respectively.